GATE EC Digital Circuits Formula Sheet

Organised by the official GATE 2027 EC syllabus, Section 5: Digital Circuits. Each worked example was checked in code. Practise these: GATE EC Digital Circuits previous year questions.

Number representations and combinatorial circuits

Syllabus: Binary, integer and floating-point numbers. Boolean algebra, minimization of functions using Boolean identities and Karnaugh map, logic gates and their static CMOS implementations, arithmetic circuits, code converters, multiplexers, decoders.

Two's complement

-2^{n-1} \le x \le 2^{n-1} - 1, \qquad -x = \bar{x} + 1

\begin{aligned} -2^{n-1} &\le x \\ &\le 2^{n-1} - 1, \\ -x &= \bar{x} + 1 \end{aligned}

Symbols

$n$ : number of bits
$\bar{x}$ : x with every bit inverted

Applies when

Signed integers in n bits. The leading bit has weight −2^(n−1). Adding two numbers of the same sign overflows if the result's sign differs.

Common mistake

Thinking the range is symmetric: 8 bits go from −128 to +127, and −128 has no positive partner.

Worked example

The 8-bit pattern 11110110: -10

IEEE 754 single precision

x = (-1)^s \times 1.f \times 2^{\,e - 127}

\begin{aligned} x &= (-1)^s \\ &\quad \times 1.f \\ &\quad \times 2^{\,e - 127} \end{aligned}

Symbols

$s$ : sign bit
$e$ : 8-bit biased exponent, 1 to 254 for normal numbers
$f$ : 23-bit fraction

Applies when

Normal numbers. e = 0 gives zero and subnormals (0.f × 2^(−126)); e = 255 gives infinity and NaN.

Common mistake

Forgetting the hidden leading 1, or the bias of 127.

Worked example

s = 0, e = 1000 0001, f = 0100 0...0: 5 (1.25 × 2²)

Boolean identities

\overline{A + B} = \bar A\,\bar B,\quad \overline{AB} = \bar A + \bar B,\quad AB + \bar A C + BC = AB + \bar A C,\quad A + \bar A B = A + B

\begin{aligned} \overline{A + B} &= \bar A\,\bar B, \\ \overline{AB} &= \bar A + \bar B, \\ AB + \bar A C + BC &= AB + \bar A C, \\ A + \bar A B &= A + B \end{aligned}

Symbols

$A, B, C$ : Boolean variables

Applies when

Any Boolean expressions. The third is the consensus theorem: the BC term is redundant.

Common mistake

Applying De Morgan without changing the operator: the complement of a sum is a product of complements.

Worked example

Rows of the truth table where AB + A′C + BC equals AB + A′C: 8 (all 8)

Full adder and ripple-carry delay

S = A \oplus B \oplus C_{in}, \qquad C_{out} = AB + C_{in}(A \oplus B), \qquad t_{ripple} \approx n\, t_{carry}

\begin{aligned} S &= A \oplus B \oplus C_{in}, \\ C_{out} &= AB + C_{in}(A \oplus B), \\ t_{ripple} &\approx n\, t_{carry} \end{aligned}

Symbols

$C_{in}, C_{out}$ : carry in and out
$t_{carry}$ : carry delay of one stage (s)
$n$ : number of bits

Applies when

A ripple-carry adder's worst case is a carry that travels through every stage; a carry-lookahead adder avoids it.

Common mistake

Counting the sum delay of every stage: only the carry ripples; the last sum adds one gate delay at the end.

Worked example

8-bit ripple-carry adder with 2 ns per carry stage: 16 ns

Multiplexers and decoders

2^n\!:\!1 \text{ MUX: } n \text{ select lines}; \qquad n\text{-to-}2^n \text{ decoder: } 2^n \text{ outputs, one per minterm}

\begin{gathered} 2^n\!:\!1 \text{ MUX: } n \text{ select lines} \\ n\text{-to-}2^n \text{ decoder: } 2^n \text{ outputs,} \\ \text{one per minterm} \end{gathered}

Symbols

$n$ : number of select or input lines

Applies when

Any function of n variables fits a 2^n : 1 MUX with constants on the inputs, or a 2^(n−1) : 1 MUX with the last variable (or its complement) on the inputs.

Common mistake

Thinking an n-variable function needs a 2^n : 1 MUX: one variable can go on the data inputs.

Worked example

A 16 : 1 multiplexer: 4 select lines

Dynamic power of CMOS logic

P_{dyn} = \alpha\, C_L V_{DD}^2 f

Symbols

$\alpha$ : activity factor: fraction of clock cycles with a 0 to 1 output transition
$C_L$ : switched load capacitance (F)
$f$ : clock frequency (Hz)

Applies when

Switching power of static CMOS; static (leakage) and short-circuit power are extra.

Common mistake

Dropping the square on

V_{DD}

: halving the supply cuts dynamic power to a quarter.

Worked example

α = 0.1,

C_{L}

= 10 pF,

V_{DD}

= 1.8 V, f = 100 MHz: 0.324 mW

Sequential circuits

Syllabus: Latches and flip-flops, counters, shift-registers, finite state machines, propagation delay, setup and hold time, critical path delay.

Counters

\text{mod-}N:\ \lceil \log_2 N \rceil \text{ flip-flops}; \qquad \text{ring: } N \text{ states with } N; \qquad \text{Johnson: } 2N \text{ states with } N

\begin{aligned} \text{mod-}N:\ \lceil \log_2 N \rceil \text{ flip-flops}; \\ \text{ring: } N \text{ states with } N; \\ \text{Johnson: } 2N \text{ states with } N \end{aligned}

Symbols

$N$ : number of states, or of flip-flops for ring and Johnson counters

Applies when

A mod-N counter divides the clock frequency by N at its last output.

Common mistake

Using a ring counter's count for a Johnson counter: N flip-flops give 2N states in a Johnson counter.

Worked example

A decade (mod-10) counter: 4 flip-flops

Setup and hold timing

T_{clk} \ge t_{clk\to q} + t_{comb,\max} + t_{setup}, \qquad t_{clk\to q} + t_{comb,\min} \ge t_{hold}

\begin{aligned} T_{clk} &\ge t_{clk\to q} \\ &\quad + t_{comb,\max} \\ &\quad + t_{setup}, \\ &t_{clk\to q} + t_{comb,\min} \\ &\quad \ge t_{hold} \end{aligned}

Symbols

$t_{clk\to q}$ : flip-flop clock-to-output delay (s)
$t_{comb}$ : logic delay between the flip-flops (s)
$t_{setup}, t_{hold}$ : the receiving flip-flop's setup and hold times (s)

Applies when

Flip-flops on the same ideal clock. Clock skew adds to one side or the other.

Common mistake

Trying to fix a hold violation by slowing the clock: hold doesn't depend on the clock period.

Worked example

t_{clk}

→q = 1 ns,

t_{comb}

,max = 5 ns,

t_{setup}

= 0.5 ns: the highest clock frequency: 153.8 MHz

Ripple counter speed

f_{\max} = \frac{1}{n\, t_{pd}}

Symbols

$n$ : number of flip-flops
$t_{pd}$ : propagation delay of each (s)

Applies when

Asynchronous (ripple) counters, where each flip-flop clocks the next, and the count is read after it settles.

Common mistake

Using a single flip-flop's delay: the last output settles n delays after the clock edge.

Worked example

4-bit ripple counter, 10 ns per flip-flop: 25 MHz

Data converters

Syllabus: Sample and hold circuits, ADCs and DACs.

DAC output and resolution

V_{out} = V_{ref}\,\frac{D}{2^n}, \qquad \Delta = \frac{V_{ref}}{2^n}

\begin{aligned} V_{out} &= V_{ref}\,\frac{D}{2^n}, \\ \Delta &= \frac{V_{ref}}{2^n} \end{aligned}

Symbols

$D$ : input code, 0 to 2^n − 1
$n$ : number of bits
$\Delta$ : step size, one LSB (V)

Applies when

Binary-weighted or R-2R DAC with full scale

V_{ref}

(1 − 2^(−n)). Some texts divide by 2^n − 1 instead; check which the question uses.

Common mistake

Using 2^n − 1 or 2^n inconsistently with the question's definition of full scale.

Worked example

8 bits,

V_{ref}

= 5.12 V, D = 100: 2 V

ADC quantisation and SQNR

\Delta = \frac{V_{FS}}{2^n}, \qquad \sigma_q^2 = \frac{\Delta^2}{12}, \qquad \text{SQNR} = 6.02n + 1.76\ \text{dB}

\begin{aligned} \Delta &= \frac{V_{FS}}{2^n}, \\ \sigma_q^2 &= \frac{\Delta^2}{12}, \\ \text{SQNR} &= 6.02n + 1.76\ \text{dB} \end{aligned}

Symbols

$V_{FS}$ : full-scale range (V)
$\sigma_q^2$ : quantisation noise power

Applies when

The SQNR formula is for a full-scale sinusoid and a uniform quantiser.

Common mistake

Using 6n dB with no 1.76: it matters when solving for n from an SNR.

Worked example

A 10-bit ADC: 61.96 dB

ADC architectures

\text{flash: } 2^n - 1 \text{ comparators}; \qquad \text{successive approximation: } n \text{ clock cycles}; \qquad \text{dual slope: up to } 2^{n+1} \text{ cycles}

\begin{gathered} \text{Flash: } 2^n - 1 \text{ comparators} \\ \text{Successive approximation:} \\ n \text{ clock cycles} \\ \text{Dual slope: up to } 2^{n+1} \text{ cycles} \end{gathered}

Symbols

$n$ : resolution in bits

Applies when

Flash is the fastest and largest; successive approximation does one bit per cycle; dual slope is slow but rejects noise.

Common mistake

Saying 2^n comparators for a flash ADC: the 2^n levels need 2^n − 1 thresholds.

Worked example

An 8-bit flash ADC: 255 comparators

Semiconductor memories and computer organisation

Syllabus: ROM, SRAM, DRAM. Machine instructions and addressing modes, ALU, data-path and control unit, instruction pipelining.

Memory size and address lines

\text{capacity} = 2^a \times w \text{ bits}, \qquad a = \log_2(\text{number of words})

\begin{gathered} \text{capacity} = 2^a \times w \text{ bits} \\ a = \log_2(\text{number of words}) \end{gathered}

Symbols

$a$ : number of address lines
$w$ : word length (bits)

Applies when

Each address selects one word. A 6-transistor SRAM cell holds 1 bit; a DRAM cell is one transistor and one capacitor, and needs refreshing.

Common mistake

Counting address lines from the total bits instead of the number of words.

Worked example

A 64K × 8 memory: 16 address lines

Pipeline speed-up

T_{pipe} = (k + n - 1)\,\tau, \qquad S = \frac{n k}{k + n - 1} \to k \text{ as } n \to \infty

\begin{aligned} T_{pipe} &= (k + n - 1)\,\tau, \\ S &= \frac{n k}{k + n - 1} \\ &\to k \text{ as } n \\ &\to \infty \end{aligned}

Symbols

$k$ : number of pipeline stages
$n$ : number of instructions
$\tau$ : stage time (s)

Applies when

Equal stage times and no stalls. Hazards and unequal stages lower the speed-up.

Common mistake

Claiming a speed-up of k for a short run: the pipeline takes k − 1 cycles to fill.

Worked example

k = 5, n = 100: 4.81

Practise these: GATE EC Digital Circuits previous year questions

Source for the section headings: the official GATE 2027 EC syllabus, IIT Madras. The formulas, examples and notes are Studyloaf's own.

GATE EC Digital Circuits Formula Sheet

Number representations and combinatorial circuits

Two's complement

IEEE 754 single precision

Boolean identities

Full adder and ripple-carry delay

Multiplexers and decoders

Dynamic power of CMOS logic

Sequential circuits

Counters

Setup and hold timing

Ripple counter speed

Data converters

DAC output and resolution

ADC quantisation and SQNR

ADC architectures

Semiconductor memories and computer organisation

Memory size and address lines

Pipeline speed-up

Other GATE EC formula sheets