How Do You Calculate Setup and Hold Slack for a Flip-Flop Path?

Studyloaf Team•October 10, 2026•Last verified October 10, 2026•7 min read

Setup slack is the time to spare before the next clock edge: (T + skew) − (tcq,max + tcomb,max + tsetup), using the slowest delays. Hold slack is the margin after the same edge: (tcq,min + tcomb,min) − (thold + skew), using the fastest delays and no clock period at all. For a 5 ns clock with the capture clock 0.2 ns late, the worked path below has 0.9 ns of setup slack and 0.05 ns of hold slack, so it meets timing and could run up to 243.9 MHz.

What you'll learn

  • What setup time, hold time, clock-to-Q delay and skew each mean, with the sign convention for skew
  • Where the setup and hold formulas come from, using the clock edges
  • A fully worked path with every delay given, plus the maximum clock frequency
  • Why a faster or slower clock cannot fix a hold violation
  • How skew trades setup slack against hold slack

What goes into the two checks?

Data leaves the launch flip-flop FF1 a clock-to-Q delay tcq after a clock edge, passes through combinational logic, and must be captured by FF2. FF2 needs its input stable for tsetup before its clock edge (setup time) and for thold after it (hold time). Every delay has a slowest value (propagation delay) and a fastest value (contamination delay), because different inputs take different paths through the logic. Setup is a race the data must win, so it uses the slowest values; hold is a race the data must not win too early, so it uses the fastest values.

Conventions used here

One clock of period T feeds both flip-flops. Skew is the clock's arrival time at the capture flip-flop minus its arrival time at the launch flip-flop, so positive skew means the capture clock is late. Positive slack meets the constraint and negative slack is a violation. Some textbooks define skew the other way round; flip the sign of the skew terms if a question does.

Where do the formulas come from?

Setup: data launched by FF1's edge at time 0 arrives at FF2 by tcq,max + tcomb,max at the latest. FF2 captures it on its next edge, which arrives at T + skew, and needs it there tsetup earlier. So the data is in time if tcq,max + tcomb,max ≤ T + skew − tsetup, and setup slack is the difference. Hold: the same launch edge also reaches FF2 at time skew, and FF2 is still holding the previous data until thold after that. The new data, arriving as early as tcq,min + tcomb,min, must not get there before skew + thold. So hold slack is (tcq,min + tcomb,min) − (thold + skew). The clock period never appears, because both events come from the same edge.

Worked example: a 5 ns clock with 0.2 ns of skew

A register-to-register timing path with clock skewFlip-flop FF1 launches data through combinational logic into flip-flop FF2. FF1 has clock-to-Q delay 0.3 to 0.4 nanoseconds, the logic 0.2 to 3.6 nanoseconds, and FF2 needs 0.3 nanoseconds setup and 0.25 nanoseconds hold. Both share a 5 nanosecond clock, which reaches FF2 0.2 nanoseconds after FF1.FF1tcq 0.3–0.4logicmin 0.2max 3.6FF2su 0.3h 0.25clock, T = 5 nsarrives 0.2 ns laterall times in ns
The path: FF1's clock-to-Q delay is 0.3 ns minimum and 0.4 ns maximum, the logic 0.2 ns minimum and 3.6 ns maximum, and FF2 needs 0.3 ns setup and 0.25 ns hold. The clock period is 5 ns and the clock reaches FF2 0.2 ns after FF1.
  • Setup slack = (5 + 0.2) − (0.4 + 3.6 + 0.3) = 5.2 − 4.3 = 0.9 ns. Positive, so the setup check passes.
  • Hold slack = (0.3 + 0.2) − (0.25 + 0.2) = 0.5 − 0.45 = 0.05 ns. Positive, but only just.
  • Minimum clock period: set the setup slack to zero, T = 0.4 + 3.6 + 0.3 − 0.2 = 4.1 ns, so fmax = 1 ÷ 4.1 ns = 243.9 MHz.
  • For comparison, with zero skew the setup slack would be 0.7 ns, the hold slack 0.25 ns and the minimum period 4.3 ns.
Setup and hold slack against clock periodSetup slack rises one for one with the clock period, from minus 0.6 nanoseconds at 3.5 nanoseconds to 1.9 at 6 nanoseconds, crossing zero at the minimum period of 4.1 nanoseconds and reaching 0.9 at the 5 nanosecond design period. Hold slack is a flat 0.05 nanoseconds at every period, because the clock period does not appear in the hold check.3.544.555.56-0.500.511.5clock period T (ns)slack (ns)setup 0.9 at 5 nsTmin = 4.1 nshold 0.05 (dashed)
Slack against clock period for this path. Setup slack rises one for one with T and crosses zero at 4.1 ns; hold slack stays at 0.05 ns whatever the period.

Why can't the clock period fix a hold violation?

Because T is not in the hold formula. Suppose the shortest path through the logic were 0.1 ns instead of 0.2 ns. Hold slack becomes (0.3 + 0.1) − (0.25 + 0.2) = −0.05 ns, a violation at every clock frequency: slowing the clock gives the data more time to arrive, which only helps setup. A hold violation has to be fixed in the path itself, typically by adding a delay buffer to the short path. Here a 0.1 ns buffer restores the hold slack to +0.05 ns, and as long as the buffer is not on the slowest path, the setup slack is unaffected. Reducing the skew also helps hold.

How does skew trade setup against hold?

Positive skew delays the capture edge, which gives the slow path more time (setup slack up by the skew) but also keeps the old data in demand longer (hold slack down by the skew). In the example, 0.2 ns of positive skew moved setup slack from 0.7 to 0.9 ns and hold slack from 0.25 to 0.05 ns. Negative skew does the opposite.

Common mistakes

  • Using maximum delays in the hold check or minimum delays in the setup check.
  • Putting the clock period into the hold check, then trying to fix hold by changing the frequency.
  • Getting the skew sign backwards: with skew defined as capture minus launch, it adds to the setup side and subtracts from the hold side.
  • Forgetting tcq and adding only the logic delay.
  • Reading a small positive slack as a failure. Any slack of zero or more meets the constraint.

Check your understanding

  • Q1. The same path is clocked at T = 4 ns. What is the setup slack? Answer: (4 + 0.2) − 4.3 = −0.1 ns, a violation.
  • Q2. The skew is −0.2 ns instead (capture clock early). What are the setup and hold slacks at T = 5 ns? Answer: setup (5 − 0.2) − 4.3 = 0.5 ns; hold 0.5 − (0.25 − 0.2) = 0.45 ns.
  • Q3. At 200 MHz with +0.2 ns skew, what is the largest maximum logic delay that still meets setup? Answer: 5 + 0.2 − 0.4 − 0.3 = 4.5 ns.

Related

Official source

Last verified

The GATE 2027 EC syllabus lists propagation delay, setup and hold time and critical path delay under Section 5, Digital Circuits (checked against the official PDF from IIT Madras on 10 October 2026). Every slack value was computed in exact arithmetic in code.

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