Why Does an Op-Amp Integrator Saturate, and How Long Does It Take?

Studyloaf Team•October 10, 2026•Last verified October 10, 2026•7 min read

Because an ideal integrator's gain at DC is infinite: any constant input, however small, makes the output ramp at a steady rate until it reaches a supply rail. The time it takes is the rail voltage times RC divided by the input, so a 0.5 V step into R = 10 kΩ and C = 100 nF ramps the output at −500 V/s and saturates it at −12 V after 24 ms. A resistor across the capacitor caps the DC gain, which stops small offsets from saturating it but not a large DC input.

What you'll learn

  • How the inverting integrator turns an input voltage into a ramp, and the conventions used
  • How to compute the time to saturation, with a worked example checked by simulation
  • Why even a 2 mV input offset eventually saturates an ideal integrator
  • How a feedback resistor Rf limits the drift, and what it costs
  • Three quick questions to check the arithmetic

How does the integrator work?

In the inverting integrator the input voltage drives a resistor R into the op-amp's inverting input, a capacitor C connects that input to the output, and the non-inverting input is grounded. With negative feedback and an ideal op-amp, the inverting input sits at 0 V (a virtual earth), so the input current is vin ÷ R. None of it enters the op-amp, so all of it charges C, and the output must move to keep the inverting input at 0 V: dvout/dt = −vin ÷ (RC). Integrating, vout(t) = −(1/RC) ∫ vin dt + vout(0).

Conventions used here

An ideal op-amp in every respect except that its output cannot go beyond ±12 V (ideal rails), the capacitor starts discharged so vout(0) = 0, and the integrator is inverting, so a positive input drives the output negative.

Inverting op-amp integrator with an optional feedback resistorThe input vin, a 0.5 volt step, drives a 10 kilohm resistor R into the inverting input. A 100 nanofarad capacitor C connects the output back to the inverting input, and a 1 megohm resistor Rf, the fix discussed in the post, can be added across C. The non-inverting input is grounded. The output saturates at plus or minus 12 volts.vinR = 10 kΩC = 100 nFRf = 1 MΩ (fix)−+voutrails ±12 V
The inverting integrator used in the example: R = 10 kΩ, C = 100 nF, rails at ±12 V. The 1 MΩ resistor Rf across C is the fix discussed later; leave it out for the first calculation.

Worked example: a 0.5 V step

  • Time constant: RC = 10 kΩ × 100 nF = 1 ms.
  • Ramp rate: dvout/dt = −0.5 V ÷ 1 ms = −500 V/s, a straight line downwards from 0 V.
  • Time to reach the −12 V rail: t = 12 V ÷ 500 V/s = 24 ms.
  • After that the output stays stuck at −12 V. The op-amp can no longer hold its inverting input at 0 V, so the circuit has stopped integrating.
  • A step-by-step numerical simulation of the capacitor current, at 1 µs resolution, reaches the rail at the same 24.0 ms.
Computed integrator output for a 0.5 volt input stepOutput voltage against time from 0 to 40 milliseconds. The ideal integrator ramps down at 500 volts per second and hits the minus 12 volt rail at 24 milliseconds. With Rf of 1 megohm across C the output heads for minus 50 volts along an exponential with a 0.1 second time constant, so it still saturates, slightly later, at 27.4 milliseconds.010203040-12-8-40time (ms)vout (V)24 ms27.4 mssolid: ideal, −500 V/sdashed: with Rf = 1 MΩ
The computed output for a 0.5 V step. The ideal integrator (solid) hits −12 V at 24 ms. With Rf = 1 MΩ across C (dashed) the curve bends slightly but still saturates, at 27.4 ms.

Why does it drift even with the input grounded?

A real op-amp has an input offset voltage: it behaves as if a small DC source Vos sat in series with one input. Suppose Vos = 2 mV, an illustrative value. With the input grounded, the integrator sees that 2 mV as a constant input and ramps at 2 mV ÷ 1 ms = 2 V/s. It reaches a 12 V rail after 6 s, with nothing connected to its input at all. Input bias current flowing through R into C causes the same kind of slow drift. In practice an ideal integrator is only usable if something resets the capacitor or limits its DC gain.

How does a resistor across C fix the drift?

Put Rf in parallel with C. At DC the capacitor is open, so the circuit is an inverting amplifier with gain −Rf ÷ R. With Rf = 1 MΩ that is −100, and the 2 mV offset now produces a fixed output error of (1 + Rf/R) × Vos = 101 × 2 mV = 0.202 V instead of a ramp to the rail. The price is that the circuit only integrates well above its corner frequency, 1/(2πRfC) = 1.59 Hz. At 1 kHz its gain differs from an ideal integrator's by about 0.0001%, but at frequencies near or below 1.59 Hz it behaves like a plain amplifier.

Does Rf stop the 0.5 V step from saturating?

No. With Rf the step response is vout(t) = −(Rf/R) × 0.5 V × (1 − e^(−t/τ)), with τ = RfC = 0.1 s. The output heads for −100 × 0.5 = −50 V, well past the rail, so it still saturates, just slightly later: solving −50(1 − e^(−t/0.1)) = −12 gives t = 0.1 × ln(50/38) = 27.4 ms. Rf protects against small, unwanted DC; a large intended DC input still needs a larger RC, a smaller input, or a reset. A 10 mV step, by contrast, settles harmlessly at −1 V.

Common mistakes

  • Dropping the minus sign. The inverting integrator ramps opposite to the input.
  • Mixing units in RC: 10 kΩ × 100 nF is 1 ms, not 1 s.
  • Forgetting the initial capacitor voltage, which shifts the whole ramp.
  • Expecting Rf to prevent saturation for any input. It only bounds the DC gain at −Rf ÷ R.
  • Treating a real integrator as ideal at very low frequencies, where an added Rf turns it into an amplifier.

Check your understanding

  • Q1. The same integrator (no Rf) gets a 1 V step. When does it saturate? Answer: at 1 V ÷ 1 ms = 1000 V/s, it reaches 12 V after 12 ms.
  • Q2. The input is a ±0.5 V square wave at 1 kHz. What is the peak-to-peak output? Answer: each 0.5 ms half-cycle moves the output by 0.5 V × 0.5 ms ÷ 1 ms = 0.25 V, so a 0.25 V peak-to-peak triangle.
  • Q3. C is changed to 1 µF and the input is the 0.5 V step again. When does it saturate? Answer: RC = 10 ms, so the ramp is 50 V/s and it takes 240 ms.

Related

Official source

Last verified

The GATE 2027 EC syllabus lists op-amp circuits, including integrators, under Section 4, Analog Circuits (checked against the official PDF from IIT Madras on 10 October 2026). The saturation times were computed from the formulas and checked with a numerical simulation in code; the 2 mV offset is an illustrative value, not a figure for any particular op-amp.

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