Verilog quiz
A Verilog quiz on assignments, latches, widths, state machines, clock domain crossing and testbench races: Quick 5 or up to 15 questions, an optional timer and an explanation after each answer.
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About the Verilog quiz
Choose how many of the 15 questions in the Verilog bank you want and, if you like, a time limit of 5, 10 or 15 minutes, or tap Quick 5 for five questions with no clock. Questions come one at a time in a shuffled order, so a second attempt doesn't repeat the same sequence. After each answer the explanation opens straight away, and the results list every question with its explanation, including the ones you got right. It's built for electrical and electronics engineering students and new digital design engineers who want to check a topic area quickly or test it in one sitting.
What the 15 questions cover
- Blocking and nonblocking assignments
- Latch inference and sensitivity lists
- Bit widths, shifts and the === operator
- Moore and Mealy state machines and their encoding
- Clock domain crossing and synchronizers
- SystemVerilog always_ff and testbench races
No account is needed. With a time limit, the quiz ends when the clock runs out and anything unanswered shows as skipped. Your score isn't compared with anyone else's, so it's an honest read on what you know right now.