Find the bug
Each puzzle is a short Verilog or SystemVerilog module with one mistake that compiles but misbehaves. Click the line you think is wrong to see the answer, why it's a bug and the fix.
A 3-way mux
What the 24 puzzles cover
- Latches: A 3-way mux, Clamp to a limit, Decode two flags
- Blocking in clocked blocks: A two-stage synchronizer, Pipelined add, Counter with a wrap flag
- Width mismatches: 8-bit adder with carry, Timeout after 1000 cycles, Load a constant
- Missing resets: Two-state FSM, Valid and data registers
- Races: Swap two registers, Testbench drives on the edge
- Clock domain crossing: Bring a button into the clock domain, Pass a counter to another clock, Fast pulse to a slow clock
- Combinational logic: AND-OR gate, Two-step combinational logic, Clear and increment
- State machines: Three-state FSM, 2-bit state
- Arithmetic: Check for a negative sample, Divide the clock by 10
- SystemVerilog: A flag register, One-hot select
How the puzzles are checked
Every buggy module and every fixed version is compiled with Icarus Verilog and linted with Verilator (all warnings on) before it is published. Where Verilator catches the bug, the answer names its warning, and the fixed version is checked to be free of it. Clock domain crossing and race bugs pass lint, which is why they are worth learning to spot by eye. Your progress is kept on this device only.