Posts tagged “verilog”

3 posts.

What Is the Difference Between Blocking and Nonblocking Assignments in Verilog?

Blocking (=) updates at once; nonblocking (<=) waits until every clocked block has read its inputs. Why a shift register with = becomes one flip-flop.

7 min read

How Do You Design a Finite State Machine in Verilog, With a Testbench?

A 1011 sequence detector as a Moore FSM in three blocks (state, next state, output), checked against a reference model for 1000 random bits.

9 min read

Why Does My Verilog always Block Infer a Latch?

A combinational always block infers a latch when a path leaves an output unassigned, so it must hold its old value. How to spot it, and the fix.

6 min read